Senior FPGA Design Engineer

Saifee Recruiting

San Diego

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Part Time

Travel not required

$134,000 - $180,000

Job Description

Our company brings together the most creative minds in science, technology, and engineering to develop lithography systems that are key to producing faster, cheaper, more energy-efficient semiconductor products. We design, develop, integrate, market and service these advanced machines, which enable our customers - the world’s leading chipmakers – to reduce the size and increase the functionality of their microchips, which in turn leads to smaller, more powerful consumer electronics. Our company is headquartered in Veldhoven, the Netherlands, and has 18 office locations around the United States. We are currently hiring for senior level FPGA Design engineering positions for our San Diego, CA location.
If you have a passion for technology and innovation, you’ll want to check us out. Be a part of our team. Be a part of progress.

One Company, One Goal, Limitless Innovation. It's our people that make the difference.
This position requires access to controlled technology, as defined in the Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require our company to proceed with applicants who are immediately eligible to access controlled technology.

Role and responsibilities

Contribute to the specification, design, implementation, and validation of FPGAs within highly reliable electronics for the company's EUV systems. Participate in cross-functional teams and work with multiple engineering groups to outline and create FPGA designs and associated engineering documentation. Design, implement and test new FPGA features while using robust methodologies defined as a part of the design process. Work with advanced technologies including digital communication (PCIe, 1G+ Ethernet, EtherCAT, etc), photo-detectors, signal acquisition, and distributed high precision timestamping. Assist cross-functional teams with the integration of the FPGA designs into the system environment. Past experience with a variety of interfacing standards such as LVDS, LVPECL, LVCMOS required.

  • Incorporate new features and enhancements of existing design based on specification and system requirements.
  • Design and develop new protocols to ensure communication of new modules are covered utilizing existing design constraints.
  • Development of new protocols over existing design interfaces and enhancement of existing designs to include new metrics to relay between modules.
  • Ability to clearly document & communicate requirements and design details.
  • Ensure the total design meets timing, not just features added.
  • Document test plan and follow release processes.
  • Validate design interfaces in the lab.

Education and Experience

  • 5+ years’ experience in electronic design, with hands-on experience in requirements specification, detailed design, design validation and qualification
  • BSEE required, MSEE preferred,
  • Expert in Altera/Intel CAR tools, Quartus (Prime) toolset, targeting Arria10 device,
  • Expert in System Verilog for verification and VHDL for coding,
  • Expert in taking Simulink design targeting the FPGA in VHDL meeting timing budgets and LUT/LeCount constraints,
  • Strong competence of Quartus tooling for synthesis, build, timing analysis, and achieving timing resolution using Quartus tools for managing constraint (timing/placement etc.)
  • Strong competence of QuestaSim 2020.2+ for simulating designs, at module level, chip level and interchip level,
  • Expert in automated self checking test bench verification,
  • Ability to create specifications, document the design by way of memory map, block diagrams, tables, and text.
  • Ability to create specifications, document the design by way of memory map, block diagrams, tables, and text.
  • Ability to understand system requirements to formulate FPGA requirements to document the design, implement, test, simulate, verify, and validate in the lab,
  • Ability to write test plans and execute,
  • Reverse engineer VHDL to block diagrammatic view for design reviews and documentation

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